As the scale of integration improves and technolgy shrinks, the more number of transistors are being packed into a chip that increases the density of the chip. This leads to the steady growth in the operating frequency and possesing capacity per chip, resulting in increased power dissipation. In modern VLSI systems, the clock is the most important signal because it controls the rate of data processing and communication. It provides a structured framework for dealing with high-complexity digital systems. Various survey and current research indicates that clock network consumes a large part of the total chip power. It is even much more than that of the ordinary logic used in the design. This book indicates the four novel low power flip-flops collectively called novel energy recovery flip-flops to reduce the power dissipation in a clock network. The energy recovery clocked flip-flops enable energy recovery from the H-tree based clock network, resulting in significant energy saving. The energy recovery flip-flops operate with a single phase sinusoidal clock generated by an efficient power clock generator.
Modern Computers are faster, more compact and more complex than their predecessors at the cost of increased power consumption. Energy from the inputs not transferred to the outputs is dissipated as heat and in irreversible circuits, while erasing a single bit of information, according to Landauer's Principle the bit energy is dissipated as heat. So, some information about the inputs is erased every time a logic operation is performed in irreversible manner. Reversible logic is a scheme where this energy dissipation due to irreversibility is minimized or sometimes almost nullified by utilizing the bit energy of previous results. In this book the concept has been illustrated and applied to construct Ultra Low Power Arithmetic Logic Circuits.
Bose-Chaudhuri-Hocquenghem (BCH) coding based on chip communication network is proposed to achieve low latency , high throughput and optimal Energy-Performabilty trade-off. The proposed encoding and decoding scheme is applied to SOC architecture as a practical example. The proposed design improves error correction as compared to conventional schemes. The throughput of Butterfly fat tree(BFT)/BCH architecture is increased by 50%. The design decreases the latency of the network on chip by 30%. The total power consumption required to achieve the proposed design is slightly increased by 11%. The proposed design improves Perform-ability range in comparison with conventional schemes while saving energy by 5%. BCH achieves high perform-ability (0.9) at high noise effect (?N =0.135V)¬. At short wire lengths (0.05mm), BCH saves energy 5% while increasing perform-ability (0.9) and reliability.
Short-range wireless communications continually attract interest from both industry and academia, and it is changing our life in every aspect in the last decade. The design of wireless transceivers is the bottleneck for a variety applications, due to RF modeling inaccuracy, stringent FCC regulations over the transmitted power spectrum, interference, multi-path reections, modulation scheme, receiver sensitivity, and synchronization. In addition, energy efficiency is always one of the most important design goals. Ultra-Wideband(UWB) is found to be very energy-efficient due to its low duty cycle and potentially high data rate due to its wide bandwidth. However, there still remain unsolved issues with UWB transceivers, such as pulse shaping, multi-path re ections, and receiver clock synchronization. To address these, novel techniques such as wireless multi-path equaliza- tion, pulse injection-locking for receiver clock synchronization, reconfigurable pulse shaping, low power wireless clock distribution, and an ultra-low-power super- regenerative receiver are implemented and verified on silicon. Three chips are designed and verified: a 3-5GHz Impulse-Radio(IR) UWB transceiver, a 3-60GHz al
OFDM has been an attractive choice for digital modulation in the recent years due to its robustness to channel fading and invulnerability to intersymbol interference. However, to achieve an optimal performance the corresponding channel estimation scheme need to be accurate. This book focuses on the use of guard intervals between successive OFDM symbols for channel estimation. A hybrid of blind and semi-blind estimation techniques is proposed to create an energy efficient scheme that can maintain accurate channel estimation as well as a low transmission BER. Multipath fading channel are considered for performance evaluation. The proposed hybrid scheme is tested in static as well as time varying channel environments using computer simulations. Simulation results show that the proposed scheme outperforms the existing schemes on the basis of BER performance for the same SNR.
The book focuses on the applicability of sub-threshold source coupled logic ( STSCL ) for implementing digital circuits and systems that runs at very low voltage and promise to provide desirable performance with excellent energy savings for Sectors like bio-engineering and smart sensors development where energy consumption is required to be effectively low for longer battery life. Alongside achieving ultra-low power specification, the system must also be reliable, robust and perform under harsh conditions. In this paper logic gates are designed and analyzed, using STSCL, for implementation of digital sections in small sized smart-dust sensors which should operate at very small supply and consume extremely low power.
The aim of the work is to manage the energy in wireless sensor network nodes using various schemes. The following schemes have been applied for energy management in wireless sensor networks: 1. Energy efficient node deployment using multi robot scheme 2. Aggregation routing scheme 3. Increasing ray based scheme for energy efficient searching 4. Energy efficient voting scheme 5. Energy efficient polling scheme Wireless sensor
Exploration and research on new sources of energy are conducted continuously. These include the possible energy harvesting from renewable energy, including biomass. Among available biomasses, algae are considered to have very high potential due to their characteristics. Advanced energy harvesting from algae, especially for power generation, with significantly high energy efficiency are described in this book. To achieve significantly high energy efficiency, the idea of combining both exergy recovery and process integration (called as enhanced process integration, EPI) has been proposed and described. In exergy recovery, the quality of the recirculated energy remains the same, and the recovered energy can thus be used as an energy source for the subsequent process. As a result, almost all energy involved in the process can be recovered effectively and the total energy consumption can be reduced.To use the unrecoverable energy (heat) in a certain process, the idea of process integration is introduced, where the unrecovered energy (heat) from one process is used in other processes. Hence, the total energy loss in the integrated processes can be reduced.
Energy efficiency is being improved in the Internet equipment. This is becoming an increasingly important research topic, motivated by the need to reduce energy costs for Internet Service Providers, as well as increase power density to achieve more switching capacity per-rack. In this work we consider the NetFPGA platform, which is becoming an increasingly popular routing platform for networking research due to its versatility and low-cost.
This book proposes several new utility interface converters to reduce cost, harmonic contents in line currents and to increase the reliability in interconnecting renewable energy sources such as wind, solar (photovoltaic), and fuel cells to electric utility. A new third harmonic current injection technique has been presented to reduce harmonic contents in the line current of controlled converters. A low cost, high efficiency, four-switch, three-phase PWM converter has been presented to interface small wind turbine with electric utility. A modular wind energy system along with modular utility interface converter concept is presented for higher power wind energy systems with increased reliability and power quality of the power electronics converter. A combined low cost, high efficient inverter and peak power tracker has been presented for photovoltaic energy systems. A combined low cost, high efficient inverter and peak power tracker has been presented for photovoltaic energy systems. A combined low cost, high efficiency inverter and peak power tracker has been proposed. This converter operates close to the maximum power point of the photovoltaic array and forms a DC to AC inverter.
With every passing day, the Energy requirement increases. To meet these the requirements Power system is continuously operated near to its Equilibrium point, maintaining the performance and efficiency is another challenge to meet with this. Low Frequency Oscillations arises in the system due to change in load of the system. This work is all about how Neural Networks can help us to achieve all these goals keeping performance of Power System Stabilizer intact.
This work proposes a power management and control strategy for islanded microgrids, which consist of multiple electronically-interfaced distributed energy resource (DER) units, to achieve a prescribed load sharing scheme. This strategy provides 1) a power management system, 2) DER local controllers, and 3) a frequency control and synchronization scheme. This strategy is then generalized to incorporate both power-controlled and voltage-controlled DER units. To prevent DER unit trip-out or damage under short-circuit conditions, an overcurrent/overload protection scheme is also proposed. Under microgrid islanding and communication failure, there is a need to switch from an active to a latent microgrid controller. To minimize the resultant transients, control transition should be performed smoothly. Two smooth control transition techniques, based on 1) an observer and 2) an auxiliary tracking controller, are proposed to achieve a smooth control transition. Extensive case studies, based on time-domain simulations and real-time hardware-in-the-loop case studies are also conducted to demonstrate performance of the proposed method.
Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic mapping scheme over the fixed one. Results show that applications’ performance varies according to the mapping scheme used, and a dynamic mapping scheme achieves up to 2x increase in peak bandwidth utilization and around 30% higher energy efficiency than a system using only a single fixed scheme Moreover, the technique can be used to limit memory accesses into a subset of the memory devices by controlling data allocation at a finer granularity, providing a method to throttle main memory by allowing un-accessed devices to be put into power-down mode, hence saving power to meet a certain power budget.
Charge pumps are widely used in thermoelectric scavenging systems to increase the thermoelectric generator output voltage to a suitable voltage that can supply the standard integrated circuit. Threshold voltage cancellation (Vt cancellation) scheme is applied to cancel the threshold drop associated with each diode-connected device and improve charge pump performance. Applying this scheme by using the next stage higher voltage is presented. Improving the output stage using this scheme is also presented. Simulations are performed using TSMC 0.25?m CMOS technology in Spectre® .